1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and more particularly to improvements in a gate electrode of a select-transistor in a 2-transistors type flash memory.
2. Description of the Related Art
An electrically-erasable nonvolatile semiconductor memory device such as a FLASHEEPROM (Flash Electrically-Erasable Programmable Read Only Memory) comprises two sorts of transistors, the memory-transistor and the select-transistor. A plurality of memory-transistors each of which has a floating gate electrode (FGE) and a control gate electrode (CGE) are formed in a memory cell area thereof and are under control as well as selection of a select-transistor. Further, in a more practically designed FLASHEEPROM, a transistor in a logic area such as the one in a logical operation circuit is also formed on the same substrate.
For such a FLASHEEPROM as having a logic transistor on the same substrate, a gate electrode of the logic transistor and a CGE in the memory cell area are formed from the same layer in the manufacturing method generally used. Referring to the drawings, a conventional manufacturing method is described below.
FIGS. 3(1) to 3(20) are a series of schematic cross-sectional views illustrating the steps of a conventional method of manufacturing a FLASHEEPROM.
First, upon a P-type semiconductor substrate 1, a first P-well 2 and a second P-well 3 are formed in a flash memory area and a logic area, respectively. Next, a field oxide film 4 that defines areas of elements is formed, and thereafter an oxide film 5 with a thickness of 8 to 10 nm is formed on the surface of the substrate 1 by the thermal oxidation method (FIG. 3(1)). A first N.sup.- -type polysilicon 7 that is to become a FGE material in the flash memory area is formed thereon to a thickness of 150 nm. After that, by means of ion implantation, phosphorus is injected thereinto to a dopant concentration of approximately 1 to 3.times.10.sup.19 atoms /cm.sup.3 (FIG. 3(2)). Next, in order to maintain said polysilicon only on the oxide film in the flash memory area, a photoresist 6a is formed into the pattern (FIG. 3(3)) and, using this as a mask, etching is applied thereto (FIG. 3(4)).
Next, covering said polysilicon, an ONO (Oxide-Nitride-Oxide) film 8 is grown over the entire surface to a thickness of 12 to 16 nm in terms of oxide film thickness by the CVD (Chemical Vapour Deposition) method (FIG. 3(5)). Over that, a photoresist 6b is then applied and patterned so as to cover only the flash memory area (FIG. 3(6)), and thereafter etching of said ONO film is performed. At this, the oxide film 5 in the logic area is concurrently once removed (FIG. 3(7)), and a gate oxide film with a thickness of 5 nm, for example, is subsequently formed again in the logic area (FIG. 3(8)).
Over the entire surface of the substrate, a second polysilicon 9 that is to become a CGE material as well as a material for a gate electrode in the logic area is grown to a thickness of 200 nm (FIG. 3(9)). Following that, on said second polysilicon 9, a photoresist 6c is formed into the pattern of electrodes of a memory-transistor and a select-transistor in the flash memory area, and formed over the entire surface, in the logic area (FIG. 3(10)). Etching is then applied to the second polysilicon 9, the ONO film 8 in the flash memory area and the first polysilicon 7 (FIG. 3(11)).
Next, in order to form a first LDD (Lightly-Doped Drain) structure 11 in the flash memory area, arsenic (As) or phosphorus (P) is ion-implanted thereinto with a dose of approximately 1.times.10.sup.13 to 1.times.10.sup.14 atoms/cm.sup.2. For this, the entire surface of the logic area is masked with a photoresist 6d (FIG. 3(12)). After that, to form a logic-transistor, a photoresist 6e is formed into the pattern of the entire surface of the flash memory area and of the transistor of the logic area by means of patterning (FIG. 3(13)). The subsequent etching applied thereto forms a gate electrode of the transistor in the logic area (FIG. 3(14)).
Further, for the formation of a second LDD 12 in the logic area, the entire surface of the flash memory area is again covered with a photoresist 6f and, then, As or P is ion-implanted thereinto with a dose of approximately 1.times.10.sup.13 to 1.times.10.sup.14 atoms/cm.sup.2 (FIG. 3(15)).
After removing the photoresist, anoxide film is formed over the entire surface, and there from sidewalls 13 are formed on lateral faces of the electrode materials in the flash memory area and in the logic area (FIG. 3(16)). Following that, to form source-drain (SD) regions 14 in the flash memory area and in the logic area, As is ion-implanted thereinto with a dose of approximately 1.times.10.sup.15 to 5.times.10.sup.15 atoms/cm.sup.2 (FIG. 3(17)).
Next, the oxide film lying outside of the transistors is all removed by wet etching (FIG. 3(18)) and then a titanium (Ti) film 15 is grown over the entire surface (FIG. 3(19)). Finally, by performing a salicide process in which titanium is turned to silicide and removing unreacted parts of the Ti film 15 subsequently, silicide films 16 are selectively formed on the SD regions of the P-type substrate 1 as well as on the polysilicons of the transistors, and thereby a semiconductor device having a memory-transistor (Tr) and a select-transistor (Tr) in the flash memory area and a logic-transistor (Tr) in the logic area is accomplished (FIG. 3(20)).
In the flash memory formed in such a way as described above, the first polysilicon 7 for the gate electrode of the select-transistor is not N.sup.+ -type but N.sup.- -type so that holding characteristics of the flash memory does not become deteriorated. The use of N.sup.- -type, however, brings about significant gate depletion, which results in an increase in effective thickness of the oxide film and a lowering of the operational speed. Obviously with this manufacturing method, it is impossible to add the dopants to increase the dopant concentration in the first polysilicon 7 (to make it N.sup.+ -type) so that the operational speed thereof cannot be improved further. Moreover, since the first polysilicon 7 which is the gate electrode of the select-transistor is not turned to silicide and is insulated by the ONO film 8 from the second polysilicon 9 that is turned to silicide, the resistance thereof is considerable. This gives rise to a problem that the voltage applied substantially to the gate of the select-transistor varies from cell to cell and, therefore, the ON-current of the select-transistor varies with the cell.
It is reported that there have been an attempt to form a butting contact on an ONO film of a select-transistor so as to make electrical connection between the upper and the lower electrode layers. In this case, it is necessary to add the step of forming said contact into the manufacturing method thereof, which undoubtedly complicates the steps but its effect of reducing the gate resistance is not particularly promising so far.
Meanwhile, in JP-A-5-121700, with the object of lowering the resistance of the select-transistor enough to achieve a higher operational speed, there is disclosed a structure in which a select-transistor has a gate electrode formed in such a way that a silicon film either interposing a metal silicide film therebetween or having a silicide surface thereof is formed into the shape of a sidewall on the lateral face of a gate electrode of a memory-transistor, and an adjacent circuit transistor has a gate electrode formed from the same layer as said gate electrode of the select-transistor.
In the method described in said publication, however, conductive layers of polysilicon or the like must be formed twice for the formation of the gate electrode of the memory-transistor and once more for the formation of the select-transistor and the adjacent circuit transistor. Furthermore, there are problems that, because of an insulating film present between the select-transistor and the memory-transistor, no channel is formed under that insulating film and that the gate oxide film of the select-transistor becomes thicker than the gate oxide film of the memory-transistor, which inevitably hinders the improvement of the operational speed.
Further, in JP-A-9-181282, there is disclosed a method of manufacturing a flash memory element, wherein, after a first polysilicon such as described above and an ONO film are formed, the ONO film lying in a select-transistor area and an adjacent circuit transistor area is removed by means of photolithography, and thereafter a second polysilicon is grown and, its surface being turned to silicide, patterning is applied thereto to form the shape of gate electrodes of a memory-transistor, a select-transistor and an adjacent circuit transistor, and then the ion implantation is carried out to form source-drain regions. In this method, the structure of the select-transistor is formed by patterning that is performed when a floating gate and a control gate of the select-transistor are directly contacted with each other. This produces an effect of lowering the gate resistance and, thus, making formation of a buttering contact as described above unnecessary.
In this method, however, concentrations of the implanted dopants are different between the floating gate and the control gate, while they are in contact with each other, so that the depletion of the underlying floating gate cannot be eliminated thoroughly. In general, the dopant concentration within a polysilicon layer is made uniform through thermal diffusion. In the case that a polysilicon layer is laid over another polysilicon layer, however, the surface of the lower layer is exposed to the air during the step of forming the upper layer, which leads to the formation of a thin natural oxidation film. Though 1 to 2 nm thick at the most, this natural oxidation film makes the dopant diffusion still slower by its presence. In addition, when two layers of polysilicon are formed, the grain boundaries of polysilicon layers do not usually meet on the composition plane and this further hinders the dopant diffusion. For instance, if the RTA (Rapid Thermal Annealing) treatment performed at 1020.degree. C. for 10 seconds or so is sufficient for a single-layered polysilicon, the RTA treatment at the same temperature must be carried out for as long as 40 seconds for a double-layered polysilicon such as the one described herein. In other words, to attain diffusion within the gate polysilicon in this instance, while it takes 10 seconds in a single layer, it requires 40 seconds in a double layer. Consequently, in a transistor with a double-layered structure, the diffusion in the transverse direction within the LDD becomes more marked and the effective channel length, shorter. In short, the double layer is not suited for the miniaturization, because of its substantial short channel effect.
Further, since the step of another photolithography is added to remove the ONO film lying in the select-transistor area and the adjacent circuit transistor area, another problem of further complicating steps also arises for this method.